{"id":70,"date":"2015-04-16T18:57:00","date_gmt":"2015-04-17T01:57:00","guid":{"rendered":"http:\/\/www.socforhpc.org\/?p=70"},"modified":"2015-06-19T17:26:09","modified_gmt":"2015-06-20T00:26:09","slug":"design-automation-for-hpc-clouds-and-server-class-socs-dac2015","status":"publish","type":"post","link":"http:\/\/www.socforhpc.org\/?p=70","title":{"rendered":"Design Automation for HPC, Clouds, and Server-Class SoCs (DAC2015)"},"content":{"rendered":"

\"Panorama_SF\"
\nSUNDAY June 07, 8:30am – 5:00pm | Room 304 (Moscone Center, San Francisco, CA)
\nTRACK: EDA
\nTOPIC AREA: SYSTEM-ON-CHIP DESIGN
\nDAC2015 Workshop Session 6W<\/a><\/p>\n

The current mainstream HPC and Cloud has relied upon Commercial off-the-Shelf (COTS) commodity building blocks to enable cost-effective design by sharing costs across a larger computing ecosystem. Modern HPC nodes use commodity chipsets and processor chips integrated together on custom motherboards. An alternative model for commodity HPC, high performance embedded, mobile and Cloud technology is emerging where the chip acts as the “silicon motherboard” that interconnects commodity Intellectual Property (IP) circuit building blocks to create a complete integrated System-on-a-Chip (SoC). This silicon-motherboard approach is still very much COTS, but the commodities are licensable IP for pre-verified circuit designs (the Lego-blocks for SoC designs) rather than the chips. By leveraging the enormous commodity IP market for design tools, processors, memory controllers, and I\/O circuit designs, a chip designer can focus their effort and NRE costs on engineering a handful of essential features that are not covered by the commodity ecosystem. This presents a new design paradigm and architecture for large-scale computing including both Clouds and HPC systems.<\/p>\n

Traditionally SoC design methods have focused on low-power consumer electronics or high performance embedded applications. But now SoC design methods are moving into high-end computing due to the emergence of embedded IP offering capable double-precision floating point, 64-bit address capability, and options for high performance I\/O and memory interfaces. System on Chip (SoC) integration is able to further reduce power, increase integration density, and improve reliability. It also enables designers to minimize off-chip I\/O by integrating application required peripheral functions, such as network interfaces and memory controllers by integrating application optimized components onto a single chip. However, existing CAD, EDA and HDL tools are primarily oriented towards consumer electronics devices, and gaps remain in the technologies for automating synthesis of components suitable for highly scalable HPC and Cloud systems. <\/p>\n

This workshop will explore the CAD, EDA and HDL tools for Server-Class SoCs that are suitable for server-class applications that range from high-performance embedded\/mobile to clouds and supercomputers. The focus of the workshop will be on tools that enable designers to rapidly prototype, simulate, and synthesize, with a much faster turn-around than we have come accustomed to for commodity server and high performance embedded\/mobile chip designs (many designs targeted at an 18 month design cycle for the hyper-competitive consumer market). <\/p>\n

This workshop builds upon the highly successful “System-on-Chip Design for HPC”<\/a> workshop that took place in August of 2014 in Denver Colorado. It is fortuitous to colocate with the Design Automation Conference (DAC) in order to maximally leverage the community of experts in Computer Automated Design (CAD) tools to tackle this challenging problem of reinventing High performance embedded, server, and data center technologies for the new century.<\/p>\n

Location<\/h3>\n

Moscone Center (Room 304)
\n747 Howard St
\nSan Francisco, CA 94103
\n